? semiconductor components industries, llc, 2007 april, 2007 -- rev. 13 1 publication order number: ncp3418/d ncp3418, ncp3418a dual bootstrapped 12 v mosfet driver with output disable the ncp3418 and ncp3418a are dual mosfet gate drivers optimized to drive the gates of both high--side and low--side power mosfets in a synchronous buck converter. each of the drivers is capable of driving a 3000 pf load with a 25 ns propagation delay and a 20 ns transition time. with a wide operating voltage range, high or low side mosfet gate drive voltage can be optimized for the best efficiency. internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both mosfets. the floating top driver design can accommodate vbst voltages as high as 30 v, with transient voltages as high as 35 v. both gate outputs can be driven low by applying a low logic level to the output disable (od) pin. an undervoltage lockout function ensures that both driver outputs are low when the supply voltage is low, and a thermal shutdown function provides the ic with overtemperature protection. the ncp3418a is identical to the ncp3418 except that there is no internal charge pump diode. the ncp3418 is pin--to--pin compatible with analog devices adp3418 with the following advantages: features ? faster rise and fall times ? internal charge pump diode reduces cost and parts count ? thermal shutdown for system protection ? integrated ovp ? internal pulldown resistor suppresses transient turn on of either mosfet ? anti cross--conduction protection circuitry ? floating top driver accommodates boost voltages of up to 30 v ? one input signal controls both the upper and lower gate outputs ? output disable control turns off both mosfets ? complies with vrm 10.x specifications ? undervoltage lockout ? thermally enhanced package available ? pb--free packages are available 341x = device code x=8or8a a = assembly location l = wafer lot y = year ww, w = work week g = pb--free package marking diagrams pin connections so--8 d suffix case 751 1 8 drvl v cc 18 pgnd od sw in drvh bst http://onsemi.com so--8 ep pd suffix case 751ac 1 8 1 8 341x alyw 341x ayww g 1 8 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information
ncp3418, ncp3418a http://onsemi.com 2 ordering information device package shipping ? ncp3418d so--8 98 units / rail ncp3418dr2 so--8 2500 / tape & reel NCP3418DR2G so--8 (pb--free) 2500 / tape & reel ncp3418adr2 so--8 2500 / tape & reel ncp3418adr2g so--8 (pb--free) 2500 / tape & reel ncp3418pdr2 so--8 ep 2500 / tape & reel ncp3418apdr2 so--8 ep 2500 / tape & reel ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d. figure 1. ncp3418/a block diagram 100 k 8 1 4 7 + -- 1.5 v nonoverlap 120 k 5 6 + -- 4v 2 3 v cc drvh bst sw drvl pgnd od in not present in the ncp3418a pin description pin symbol description 1 bst upper mosfet floating bootstrap supply. a capacitor connected between bst and sw pins holds this boot- strap voltage for the high--side mosfet as it is switched. the recommended capacitor value is between 100 nf and 1.0 m f. an external diode will be needed with the ncp3418a. 2 in logic--level input. this pin has primary control of the drive outputs. 3 od output disable. when low, normal operation is disabled forcing drvh and drvl low. 4 v cc input supply. a 1.0 m f ceramic capacitor should be connected from this pin to pgnd. 5 drvl output drive for the lower mosfet. 6 pgnd power ground. should be closely connected to the source of the lower mosfet. 7 sw switch node. connect to the source of the upper mosfet. 8 drvh output drive for the upper mosfet.
ncp3418, ncp3418a http://onsemi.com 3 maximum ratings rating value unit operating ambient temperature, t a 0to85 c operating junction temperature, t j (note 1) 0to150 c package thermal resistance: so--8 junction--to--case, r jc junction--to--ambient, r ja (2--layer board) 45 123 c/w c/w package thermal resistance: so--8 ep junction--to--ambient, r ja (note 2) 50 c/w storage temperature range, t s --65 to 150 c lead temperature soldering (10 sec): reflow (smd styles only) standard (note 3) lead free (note 4) 240 peak 260 peak c jedec moisture sensitivity level so--8 (240 peak profile) so--8 (260 peak profile) so--8 ep (240 peak profile) so--8 ep (260 peak profile) 1 1 1 3 -- stresses exceeding maximum ratings may damage the device. maximu m ratings are stress ratings onl y. functional operation above the recommended operating conditions is not implied. extended exposure t o stresses above the recommended operating conditions may affect device reliability. 1. internally limited by thermal shutdown, 150 cmin. 2. rating applies when soldered to an appropriate thermal area on the pcb. 3. 60 -- 180 seconds minimum above 183 c. 4. 60 -- 180 seconds minimum above 237 c. note: this device is esd sensitive. us e standard esd precautions when handling. maximum ratings pin symbol pin name v max v min v cc main supply voltage input 15 v -- 0 . 3 v bst bootstrap supply voltage input 30 v wrt/pgnd 35 v 50 ns wrt/pgnd, 15 v wrt/sw --0.3 v wrt/sw sw switching node (bootstrap supply return) 30 v -- 1 . 0 v d c --10 v< 200 ns drvh high--side driver output bst + 0.3 v 35 v 50 ns wrt/pgnd, 15 v wrt/sw --0.3 v wrt/sw drvl low--side driver output v cc +0.3v -- 0 . 3 v d c --2.0 v < 200 ns in drvh and drvl control input v cc +0.3v -- 0 . 3 v od output disable v cc +0.3v -- 0 . 3 v pgnd ground 0v 0v note: all voltages are with respect to pgnd except where noted.
ncp3418, ncp3418a http://onsemi.com 4 ncp3418--specifications (note 5) (v cc =12v,t a =0 cto+85 c, t j =0 c to +125 c unless otherwise noted.). parameter conditions symbol min typ max unit supply supply voltage range -- v cc 4.6 -- 13.2 v supply current bst=12v,in=0v i sys -- 2.0 6.0 ma od input input voltage high -- -- 2.0 -- -- v input voltage low -- -- -- -- 0.8 v input current -- -- -- 1 . 0 -- +1.0 m a propagation delay time (note 6) seefigure2 t pdlod t pdhod -- -- 40 40 60 60 ns ns pwm input input voltage high -- -- 2.0 -- -- v input voltage low -- -- -- -- 0.8 v input current -- -- -- 1 . 0 -- +1.0 m a high--side driver output resistance, sourcing current v bst -- v sw =12v(note8) -- -- 1.8 3.0 output resistance, sinking current v bst -- v sw =12v(note8) -- -- 1.0 2.5 transition times (note 6) v bst -- v sw =12v,c load =3.0nf, seefigure3 t rdrvh t fdrvh -- -- 18 10 25 15 ns ns propagation delay (notes 6 & 7) v bst -- v sw =12v t pdhdrvh t pdldrvh -- -- 30 25 60 45 ns ns low--side driver output resistance, sourcing current -- v cc =12v (note 8) -- 1.8 3.0 output resistance, sinking current -- v cc -- v sw =12v (note 8) -- 1.0 2.5 transition times t rdrvl t fdrvl c load =3.0nf, seefigure3 -- -- 16 11 25 15 ns ns propagation delay t pdhdrvl t pdldrvl seefigure3 -- -- 30 20 60 30 ns ns undervoltage lockout uvlo -- -- 3.9 4.3 4.6 v hysteresis (note 8) -- 0.5 v thermal shutdown over temperature protection (note 8) -- 150 170 c hysteresis (note 8) 20 c 5. all limits at temperature extremes are guaranteed via corre lation using standard statistical quality control (sqc). 6. ac specifications are guaranteed by c haracterization, but not production tested. 7. for propagation delays, ?t pdh ?? refers to the specified signal going high; ?t pdl ?? refers to it going low. 8. gbd: guaranteed by design; not tested in production. specifications subjec t to change without notice.
ncp3418, ncp3418a http://onsemi.com 5 figure 2. output disable timing diagram drvh or drvl od t pdlod 90% t pdhod 10% figure 3. nonoverlap timing diagram (timing is referenced to the 90% and 10% points unless otherwise noted) t fdrvh t rdrvl t pdldrvh t fdrvl t pdldrvl t pdhdrvh t rdrvh 4v t pdhdrvl drvh--sw sw drvl in 10% 10% 90% 10% 1.5 v 10% 90% 90% 90%
ncp3418, ncp3418a http://onsemi.com 6 applications information figure 4. drvh rise and drvl fall times figure 5. drvh fall and drvl rise times in drvl drvh in drvl drvh supply current (ma) fall time (ns) 0 60 in frequency (khz) 50 40 30 10 200 400 600 800 1000 1200 20 0 15 1 40 load capacitance (nf) 30 5 20 0 10 2 3 4 5 0 12 3 4 5 load capacitance (nf) 10 figure 6. rise time vs. load capacitance figure 7. fall time vs. load capacitance figure 8. v cc supply current vs. in frequency trtg t a =25 c v cc =12v c load =3.3nf i cc rise time (ns) trbg trtg trbg
ncp3418, ncp3418a http://onsemi.com 7 applications information theory of operation the ncp3418 and ncp3418a are single phase mosfet drivers optimized for driving two n--channel mosfets in a synchronous buck converter topology. the ncp3418 features an internal diode, while the ncp3418a requires an external bst diode for the floating top gate driver. a single pwm input signal is all that is required to properly drive the high--side and the low--side mosfets. each driver is capable of driving a 3.3 nf load at frequencies up to 500 khz. low--side driver the low--side driver is designed to drive a ground--referenced low r ds(on) n--channel mosfet. the voltage rail for the low--side driver is internally connected to the v cc supply and pgnd. when the ncp3418 is enabled, the low--side driver?s output is 180 _ out of phase with the pwm input. when the device is disabled, the low--side gate is held low. high--side driver the high--side driver is designed to drive a floating low r ds(on) n--channel mosfet. the bias voltage for the high side driver is developed by a bootstrap circuit referenced to sw. the bootstrap capacitor should be connected between the bst and sw pins. the bootstrap circuit comprises an internal or external diode, d1 (in which the anode is connected to v cc ), and an external bootstrap capacitor, c bst . when the ncp3418 is starting up, the sw pin is at ground, so the bootstrap capacitor will charge up to v cc through d1. when the pwm input goes high, the high--side driver will begin to turn on the high--side mosfet by pulling charge out of c bst . as the high--side mosfet turns on, the sw pin will rise to v in , forcing the bst pin to v in +v cc , which is enough gate--to--source voltage to hold the mosfet on. to complete the cycle, the high--side mosfet is switched off by pulling the gate down to the voltage at the sw pin. when low--side mosfet turns on, the sw pin is held at ground. this allows the bootstrap capacitortochargeuptov cc again. the high--side driver?s output is in phase with the pwm input. when the device is disabled, the high side gate is held low. safety timer and overlap protection circuit the overlap protection circuit prevents both the high--side mosfet and the low--side mosfet from being on at the same time, and minimizes the associated off times. this will reduce power losses in the switching elements. the overlap protection circuit accomplishe s this by controlling the delay from turning off the high--side mosfet to turning on the low--side mosfet. to prevent cross conduction during the high--side mosfet?s turn--off and the low--side mosfet?s turn--on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, drvh will go low after a propagation delay (t pdldrvh ), turning the high--side mosfet off. however, before the low--side mosfet can turn on, the overlap protection circuit waits for the voltage at the sw pin to fall below 4.0 v. once sw falls below the 4.0 v threshold, drvl will go high after a propagation delay (t pdhdrvl ), turning the low--side mosfet on. however, if sw does not fall below 4.0 v in 300 ns, the safety timer circuit will override the normal control scheme and drive drvl high. this will help insure that if the high--side mosfet fails to turn off it will not produce an over--voltage at the output. similarly, to prevent cross conduction during the low--side mosfet?s turn--off and the high--side mosfet?s turn--on, the overlap circuit monitors the voltage at the gate of the low--side mosfet through the drvl pin. when the pwm signal goes high, drvl will go low after a propagation delay (t pdldrvl ), turning the low--side mosfet off. however, before the high--side mosfet can turn on, the overlap protection circuit waits for the voltage at drvl to drop below 1.5 v. once this has occurred, drvh will go high after a propagation delay (t pdhdrvh ), turning the high--side mosfet on. application information supply capacitor selection for the supply input (v cc ) of the ncp3418, a local bypass capacitor is recommended to reduce noise and supply peak currents during operation. use a 1.0 to 4.7 m f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. keep the ceramic capacitor as close as possible to the v cc and pgnd pins. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and the internal (or an external) diode. selection of these components can be done after the high--side mosfet has been chosen. the bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. a minimum 50 v rating is recommended. the capacitance is determined using the following equation: c bst = q gate v bst (eq. 1) where q gate is the total gate charge of the high--side mosfet, and v bst is the voltage droop allowed on the high--side mosfet drive. for example, a ntd60n03 has a total gate charge of about 30 nc. for an allowed droop of 300 mv, the required bootstrap capacitance is 100 nf. a good quality ceramic capacitor should be used. if an external schottky diode will be used for bootstrap, it must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on sw. the average forward current can be estimated by: i f(avg) = q gate f max (eq. 2) where f max is the maximum switching frequency of the controller. the peak surge current rating should be checked in--circuit, since this is dependent on the source impedance of the 12 v supply and the esr of c bst.
ncp3418, ncp3418a http://onsemi.com 8 package dimensions soic--8 nb case 751--07 issue ah seating plane 1 4 5 8 n j x45 _ k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751--01 thru 751--06 are obsolete. new standard is 751--07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0808 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 -- x -- -- y -- g m y m 0.25 (0.010) -- z -- y m 0.25 (0.010) z s x s m ____ 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 ? mm inches ? scale 6:1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp3418, ncp3418a http://onsemi.com 9 package dimensions soic--8 ep case 751ac--01 issue b h c 0.10 d e1 a d pin one 2x 8x seating plane exposed gauge plane 14 5 8 d c 0.10 a--b 2x e b e c 0.10 2x top view side view bottom view detail a end view section a--a 8x b a--b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datumsaandbtobedetermined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 08 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc _ _ a1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* location exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 ? mm inches ? scale 6:1 7.0 0.275 2.72 0.107 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. sc illc makes no warranty, repres entation or guarantee r egarding the suitability of its produc ts for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each cus tomer application by customer?s technical experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc pr oducts are not designed, intended, or autho rized for use as components in systems i ntended for surgical implant int o the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal inj ury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, an y claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the p art. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 ncp3418/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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